Position Title: Senior Physical Design Engineer Location: San Diego OR Irvine OR San Jose CA (onsite) Full-time: Salary + Benefits + Bonuses or Contractor (corp-to-corp) Work Status: US Citizen or US Permanent Resident Responsibilities: Perform block level implementation using place and route techniques to meet area/timing and power requirements. Drive clock tree planning and implementation to achieve best energy, performance, and area. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Work directly with Synthesis/Timing Team to ensure Design closure. Manage quality deliverables for execution excellence in physical design. Requirements: Deep understanding of all aspects of Physical Design, Integration, STA, and Physical Verification. Hands-on experience in block-level floor-planning, power planning, placement, clock tree synthesis, routing, LVS/DRC/ERC, timing closure, signoff, and engineering change orders (ECO's). Knowledge and skills in optimizing PPA through floor-planning, placement and timing constraints, useful skew, and similar techniques. Experience with the Cadence digital EDA toolset (Innovus / Quantus / Tempus / Conformal). Ability to use scripting languages to automate process flow. Team player with good interpersonal and communication skills. BSEE with 8+ years of experience. Desirable Skills: MSEE with 5+ years of experience. Experience working with communications chips. Ability to be proactive and have a strategic mindset in addition to having tactical problem-solving experience. Familiarity with industry standard interfaces. #J-18808-Ljbffr Encore Semi Llc
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